Job Openings For UVM Verification Engineer In Sweden.

We are actively hiring for UVM VERIFICATION ENGINEER for SWEDEN

Remote working option enabled until the Covid-19 situation is stable globally and then travel to Sweden.

You will, as part of a project team, take ownership of the verification of particular blocks as well as system level verification within the product architecture, moving through all phases of the design and verification flow

Requirements- Must Have:

Min 8 + years’ exp of ASIC / FPGA verification.

Block/ System/ Sub-system verification using SV+UVM.

 4+ years of exp in UVM.

Scripting – Python, TCL, and/or Perl.

Good to have:

Domain competence around #BaseBand and 5G but not necessary

BackEnd Integration Experience

Knowledge in High speed interfaces like Ethernet, CPRI and switching.

Verification using SpecmanE.

Correction algorithms and Encryption algorithms.

FormalVerification and TopLevelverification.

High-Level Synthesis.

Lab measurements on FPGA platforms.

Experience in mixed-signal development.

Interested candidates pls drop a mail at surya.k@siriab.se